Low Power and Efficient Dadda Multiplier

In this study an area optimized Dadda multiplier with a data aware Brent Kung adder in the final addition stage of the Dadda algorithm for improved efficiency has been described in 45 nm technology. Currently the trend is to shift towards low area designs due to the increasing cost of scaled CMOS. An area reduced full adder is the key component in our design. It uses lesser number of gates than conventional design and hence lesser area and delay. The data aware Brent Kung adder in the final addition stage helps in reducing dynamic power as it reduces switching activity depending on the inputs. We have compared the results to the existing benchmark designs and our experimental results show that we have been capable of reducing the area by 13.011% and total power by 26.1% with only a slight increase in the delay.